Location - San Jose, CA

Duration - 3 - 6 mos CTH

Rate - Market

Skills -

Architecture Modeling/Software Engineer

Key Responsibilities:

• Develop high-level models for networking devices
• Create structural models based on architectural specifications to estimate throughput, latency, and other performance metrics
• Collaborate with system and chip architects to optimize the performance
• Design and develop architectural traffic pattern generators to test various features
• Work closely with cross-functional teams to investigate and develop algorithms and solutions to enhance system level performance
• Produce documentation, including specifications, test plans, design reviews, and technical reports. Communicate findings and recommendations to stakeholders

Qualifications:

• MSEE with at least 7+ years of experience in networking, chip architecture, or related fields
• Proven experience in designing and optimizing chip architectures, especially in networking environments
• Strong understanding of networking concepts, including Ethernet and PCIe protocols
• Proficiency in modeling languages, particularly C, C++, and scripting in Python and/or Perl
• Solid understanding of FPGA or ASIC design methodologies, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence)
• Strong analytical and problem-solving abilities, with attention to detail in debugging and troubleshooting complex networking issues
• Excellent communication skills with the ability to collaborate effectively in a team environment and present technical information to diverse audiences