A Semiconductor design company are looking for an experienced ASIC Verification Engineer to join their team, to work on a variety of cutting edge projects across various products in the Semiconductor space.

Due to stable and organic growth as a result of having a strong reputation in the industry, the business is gong from strength to strength and are keen to build on their current design expertise.

Overview:

Join our team as a Senior ASIC Verification Engineer and contribute to the success of cutting-edge ASIC projects at advanced technology nodes, reaching down to 3nm FinFET. As a crucial member of our dynamic and highly skilled team, you will play a pivotal role in ensuring the functional integrity of complex System-on-Chips (SOCs). Leverage your expertise in SystemVerilog, UVM, and scripting languages to drive prime verification activities and employ state-of-the-art methodologies and tools to validate designs.

Key Responsibilities:

Verification Activities:

• Work on verification activities for assigned blocks or entire chips, ensuring strict adherence to project timelines.
• Utilize your expertise in SystemVerilog, UVM, and scripting languages to develop robust verification environments.

Verification Environment Architecture:

• Design the verification environment architecture using UVM, with a focus on robustness and scalability.

Test Case Development:

• Document test environment associations and create comprehensive test cases to validate design functionality.

Coverage Enhancement:

• Apply constrained random verification approaches to enhance test coverage.

Lab Support:

• Provide direct support for lab bring-up, execute test cases, and troubleshoot as needed.

Analysis:

• Perform thorough code and functional coverage analysis to ensure comprehensive verification.

Key Qualifications:

Experience:

• Eight or more years of experience in ASIC verification with a proven track record of delivering successful projects.

Programming Proficiency:

• Proficient in Verilog, SystemVerilog, and other hardware description languages.
• Expertise in scripting languages.

Methodology Mastery:

• Extensive experience with OVM/UVM methodologies, showcasing a deep understanding of advanced verification techniques.

Techniques Familiarity:

• Familiarity with constrained random verification techniques, assertions, and functional coverage.

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