Physical Design Engineer – San Jose

Position Overview

This role focuses on the physical design of integrated circuits (ICs), where you will be responsible for the end-to-end implementation of physical design processes, including synthesis, floorplanning, clock tree synthesis (CTS), and place and route. You will work on high-speed designs and contribute to the development and validation of power grids and clock constraints, playing a crucial role in ensuring designs meet performance and manufacturing requirements.

Key Responsibilities

• Physical Design Implementation : Perform physical synthesis, floor planning, clock tree synthesis (CTS), place and route, and other key physical design tasks in compliance with industry standards.
• Power Grid and Clock Constraints : Develop and implement high-speed clock and power grid specifications and constraints to optimize power efficiency and design performance.
• Physical Design Verification : Debug and resolve LVS/DRC issues at both the block and chip levels using physical design verification methodologies.
• Timing and Signal Integrity : Perform static timing analysis (STA), handle clock domain crossing (CDC), and understand parasitic delays through SDF-annotated simulations.
• Mixed-Signal Environment : Work within mixed-signal environments, ensuring smooth integration between analog and digital components in the design.
• Tape-Out and Foundry Interface : Manage design tape-out processes and collaborate with foundries, ensuring a solid understanding of the semiconductor supply chain.

Required Qualifications

• Master’s degree in Electrical Engineering or Computer Engineering (MSEE/CE) or equivalent.
• At least 8 years of experience in physical design.
• Expertise in physical design methodologies, including physical-aware synthesis, floorplanning, CTS, and place and route.
• Experience with high-speed design constraints and implementation.
• Strong knowledge of power-grid development and high-speed clock constraints.
• Experience with physical design verification tools to resolve LVS/DRC issues.
• Proficiency in static timing analysis, CDC methodologies, and related tools.
• Experience with SDF-annotated simulations and understanding of parasitic delays.
• Expertise in mixed-signal design environments.
• Familiarity with tools such as Virtuoso, Caliber, and Redhawk for power analysis.
• Experience with the IC design tape-out process and semiconductor supply chain.

Preferred Qualifications

• Familiarity with backend Cadence tools.
• Deep understanding of signal integrity and power integrity in high-speed designs.
• Proactive, collaborative, and creative problem-solving approach, with a focus on innovation and consensus-building to drive optimal project outcomes.
• Strong time management, task management, and interpersonal skills