Meet the TeamnnThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.nnYour ImpactnnYou are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly, and are always focused on driving designs to closure. Responsibilities will include:nnDeveloping timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.nnCheck timing for unconstrained endpoints, no clock, etc.nnYour role may include SDC validation, CDC delay check, and SDC flow development.nnSTA runs, more specifically at scan modes along with advising the Physical Design team on best practices.nnDeveloping methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.nnMinimum QualificationsnnBachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.nnExperience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes).nnExpertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.nnProgramming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages.nnPreferred QualificationsnnMaster’s Degree in electrical or computer engineering (or other equivalent field) with 6+ years of related work experience.nnThorough understanding of noise, cross talk, OCV, Sigma effects and Liberty file formats including standard cells/memory/IO/IP modeling and its usage in the ASIC flow.nnBackground in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.nnPrior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime, Cadence CCD/Tempus.nnStrong communication skills and team player.nnWhy Cisconn#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company.nnWe even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).nnDay to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.nnBecause without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!nn#WeAreCisconnCisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.nnCisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.