10+ years of experience in RTL/Verilog writing.

Have expertise in static checking like CDC, Lint, RDC, Spyglass DFT along with module integration e

Logic design /micro-architecture /RTL coding

Expertise in Verilog & System Verilog

Experience in Synthesis /Understanding of timing concepts for ASIC is required.

Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.