The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for our custom silicon/ASIC designs, resulting in zero bugs in the final design to ensure first time silicon success.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You should be a team leader with excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks
• Ability to come with detailed test plan based on the Architecture specifications
• Good understanding and exposure to SoC designs and architectures
• 12+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge
• Candidates should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions.
• Own the DV sign-off and ensure a bug free design
• Work with the post-silicon team on debug support and to help root-cause any failures
• Have worked on wireless protocol design verification
• Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow
• Exposure to DEBUG concepts such as JTAG etc
• Comfortable with VCS/Verdi and excellent debug skills
• Logical in thinking and ability to gel well within a team
• Good communication and leadership skills
• Continuously drive methodology improvements to improve efficiency
• Mentor junior engineers to build a high performing team

PREFERRED EXPERIENCE:

• Experience in leading digital verification efforts.
• Proficient in SoC/sub-system/IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches
• Experienced with Verilog, System Verilog, C, and C++
• Worked on any High-Speed Interface like CXL/ PCIE/DDR/USB/Other, good understanding of AXI/AHB/APB Bus protocol
• Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification
• Developing UVM based verification frameworks and testbenches, processes and flows
• Good understanding and hands-on experience in the UVM concepts and System Verilog language
• Scripting language experience: Perl, Python, Make file, shell preferred.