Title: Post Silicon Validation Engineer Ethernet

Location: Santa Clara (hybrid), CA

Duration: 6 months

Duties:

• Develop and run post-silicon validation tests and associated scripts for successfully validating Ethernet network interfaces (PHY / PCS / MAC).
• Analyze and debug test failures independently to identify root cause.
• Debug complex cross-functional issues with ASIC, system hardware, and software engineers.
• Build powerful programs in Python and C to automate testing, regression, and debugging.

Skills:

• 5+ years of relevant post-silicon validation experience.
• Proficiency with lab equipment, logic analyzers, and oscilloscopes.
• Expertise in Python and C.
• Thorough understanding of Ethernet PHY / PCS / MAC standards (e.g. IEEE 802.3) and technologies.
• Proven success in functional and electrical bringup and validation of PAM4 and NRZ Ethernet interfaces on multiple ASICs.
• Hands-on experience with traffic generators such as Spirent and Ixia Demonstrated ownership and independence in planning, analyzing, debugging, driving vendors, and reporting status.
• Strong collaboration and communication skills.

Education:

BS or MS in EE, CE, or CS or equivalent experience.

Minimum Degree Required: Bachelor's Degree

Certifications & Licenses:

Proficiency with lab equipment, logic analyzers, and oscilloscopes

Preferred Skills :

5+ years of relevant post-silicon validation experience

Python and C