This innovative startup, based in Santa Clara, is focused on developing high-performance data center accelerators for the largest generative AI models. As part of the dynamic team, the Principal Architect will play a pivotal role in shaping the architecture for modern AI workloads. The architect will lead the design and development of key subsystems, including memory hierarchies, interconnects, and debug solutions. The role involves collaborating with cross-functional teams to ensure that compute architectures are optimized for performance, scalability, and efficiency, supporting the success of cutting-edge AI models.
Responsibilities:
- Lead the design of advanced memory subsystems, focusing on low-latency and high-throughput interconnects and cache hierarchies.
- Define high-speed interconnects between accelerator systems, enabling scalability and parallelism for large workloads.
- Develop and integrate robust debug subsystems to support system validation and optimization.
- Collaborate with hardware, firmware, and software teams to ensure specifications meet cross-functional requirements.
- Use SystemC models to simulate and validate architectural changes and optimize kernel performance.
Qualifications:
- MSEE with 10+ years or PhD in Electrical/Computer Engineering, specializing in SoC design, ML accelerators, system modeling, and simulation.
- Hands-on experience with datacenter-grade hardware architectures, particularly for AI/ML workloads.
- Strong understanding of operational primitives underlying modern AI models, with experience designing chip-to-chip interconnects and networking solutions (e.g., UCIe, PCIe, Ethernet).
- Proficient in writing optimized ML kernels and parallel computing techniques (assembly level, preferably RISC), and experienced with memory management schemes, on-chip and off-chip data movement.
- Experience with SystemC, Python, and C/C++ for production-level code, along with a demonstrated ability to work in a fast-paced, startup environment and contribute to open-source AI/ML projects.