||Looking for those who can work on W2||

Job details are Shared below:

Job Title: Senior ASIC Engineer, Static Timing Analysis

Location: Longmont, CO- Onsite/Hybrid (3x per week)

Job Duration: 6+m Contract with potential for conversion

Primary Skills:

• Experience with Static Timing Analysis tools
• Experience with RTL Static Analysis and Linting
• Experience with Clock Domain Crossing and Formal Verification
• Bachelor's degree required .
• Attention to the detail
• Very good communication skills (both written and verbal)
• Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)
• Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets
• Summarize the regression results periodically to track the progress.
• Able to debug the basic issues like SDC loading errors, check_timing (no_clock, unconstrained, no_clock, QoR violations)

PREFERRED EXPERIENCE:

• Minimum of 6-8 years' experience
• Worked with EDA tools that enable RTL quality checks
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Ability to multitask, ramp up quickly on new flows/tools/ideas
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable

Qualification:

• Bachelor's degree.

Please respond at the earliest to speed up the interview process. I will contact you if I need further details.

Amit Bundele

Technical Recruiter

Phone : 669-319-4167

Email :

San Jose, California