THIS IS NOT AN ENTRY LEVEL ROLE - PLEASE NO RECENT GRADUATES

DFT Engineer - all levels.

A RISC-V start up is looking for DFT Engineers of all levels. We have roles for all levels from Engineer to Senior and through to Lead/Manager positions.

The positions are available across Mountain View CA , Austin TX, Portland OR, Fort Collins CO

We have open positions for full-time roles in DFT design, ranging from unit level to chip level, encompassing various aspects of DFT design functions such as scan, MBIST, and ATPG.

Opportunities exist in both CPU and SOC DFT design and verification.

Responsibilities:

• Develop DFT strategy and methodologies
• Design DFT features
• Define test structures, debug structures, and test plans
• Oversee or create test vectors
• Collaborate with the physical design team to meet requirements
• Validate adherence to DFT requirements
• Work with designers to enhance test coverage, debug observability, and flexibility
• Verify post-PD designs against DFT requirements
• Collaborate with verification engineers and step in to run tests when needed

Requirements:

• Solid understanding of digital logic design, microprocessor, debug features, DFT architecture, CPU architecture, and microarchitecture
• Familiarity with DFT and structural debug concepts and methodologies, including JTAG, IEEE1500, MBIST, scan dump, and memory dump
• Proficiency in Verilog, experience with simulators, and waveform debugging tools
• Knowledge of Verilog/SystemVerilog
• Familiarity with Python, Shell scripting, Makefiles, and TCL (a plus)
• Strong problem-solving skills, effective written and verbal communication, excellent organization, and high self-motivation
• Ability to thrive in a team and deliver under aggressive schedules

Education and Experience:

• PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area