High Speed ASIC AI Chip Team: San Jose- In-Office Daily-

Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon.

Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems.

Synthesize Verilog RTL and build models for emulation platforms such as Zebu or Palladium.

Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges.

Automation and Methodology:

Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value.

Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation.

Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans

Preferred Qualifications:

Experience with C/C++ DPI Transactors, SystemVerilog assertions, and coverage metrics.

Proven ability to design and develop synthesizable models for emulation.

Hands-on experience with IXIA/Spirent traffic generators for networking validation.

Strong understanding of networking protocols and RFC test suites.

Familiarity with communication/interface protocols like PCIe, SPI, and JTAG.