Title :: Senior Design Verification Engineer

You will:

• Work within a small friendly team of world class design and verification engineers
• Create verification plans, develop and maintain UVM testbench components
• Write SV-UVM tests, sequences, functional coverage & assertions
• Track and report verification metrics and closure
• Participate in all stages of design specification definition providing feedback from the verification perspective
• Be responsible for the definition, effort estimation and tracking of your own work
• Participate in design and verification reviews and recommend improvements
• Contribute to team shared knowledge via open discussions and presentations
• Have full ownership of the verification of one or more modules of which you will be responsible for the delivery of verification activities