What You'll Be Doing

• Develop Clock RTL generation and distribution tools for high performance SOCs and large die size
• Core clock design, flow and verification automation for high performance chips in 3nm/5nm etc
• Design of custom clock cells for clock mesh implementatiom
• Collaborate with the Clocks, unit, post-silicon and backend teams to understand the current concerns with Clocking and come up with solutions for supporting high speed Clocking.
• Understand the physical aspects of the chip and develop better clock distribution techniques.
• Contribute to new design implementation flows.

What We Need To See

• BS or MS (preferred) degree or equivalent experience in CE or EE
• At least 10+ years of work experience.
• Strong circuit design experience
• Validated strong coding skills in C++ or other industry-standard scripting languages.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent problem solving and debugging skills.
• Strong interpersonal and collaboration skills are required.