Senior/Lead Asynchronous SRAM Design Engineer
US Citizen or US Permanent Resident
We have an immediate need for an experienced Senior SRAM IC Design Engineer who has 10+ years of experience with custom Asynchronous SRAM design. The ideal candidate has specific technical expertise in a broad range of process technologies (180nm to FinFET) and complex, high-performance circuits. Candidate must have experience in sense amp, write circuit, decoder, ATD (address transition detection), and redundancy design experience, in addition to chip level architecture and simulation experience. Candidate must also have a solid understanding of SRAM DFM and DFMEA, i.e. design risk mitigation and design yield enhancement techniques.
Responsibilities and Qualifications:
- BSEE/MSEE with 10+ years of experience in IC design, or equivalent
- Expert in custom digital circuits for SRAM design (Asynchronous required)
- Expert in using Cadence/Synopsys design flow
- Proven success with late-write SRAM architectures
- Ability to create and present design reviews, test/characterization plans
- Understanding of digital and analog/mixed signal design (digital front end and RF experience is desired)
- Proven record of technical expertise developing integrated circuit design
- Must have thorough understanding of best practices for silicon development tools and processes and must be able to support post-silicon effort to enable productization
- Strong communication, debugging and analytical skills with complex technical concepts
- Experience with a variety of manufacturing technologies and design applications preferred
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