RTL Design Engineer at Location: Sunnyvale, CA Full time position

• Digital Design Engineering/RTL Design Services:

• ASIC design and integration familiar with lint/cdc/rdc challenges, comfortable with scripting

• Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components

• Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components

• SoC-level integration

• Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation

• Design for low power and power intent design using Unified Power Format (“UPF”)

• Constraint development, synthesis, timing closure, and optimization of the design

• Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing

• Debug and bug fixes

Regards

Trevor