Job description:

• As an RTL Design Engineer you will be responsible for ASIC designs used in Memory Controllers, Video, AR, VR, or MR applications.

Responsibilities:

• Develop micro architectural document from requirements specifications.
• Extensive RTL design utilizing Verilog / SystemVerilog
• Perform basic linting and other QC
• Collaborate and support SoC integration as needed

Requirements:

• Minimum 10 years of strong experience in Digital design at RTL level using Verilog / SystemVerilog
• Experience developing micro architectural document from requirements specifications.
• Conceptual Design experience, this is not SoC integration of blocks.
• Experience applying linting and other (QC) quality checking and basic verification of designs.
• Well versed in SystemVerilog Language
• EDA tools Cadence and Synopsys
• Strong communication and collaboration skills
• Experienced with designs related to Video, AR, VR or MR.
• IP Design – similar memory controllers, Image processing IP /Design and interconnect

Preferred:

• DMA, memory controller, MIPI protocols communication
• DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces. RTL Design automation, using Python scripting.