MediaTek is a global fabless semiconductor company that enables more than 2 billion consumer products a year. We are a market leader in developing tightly-integrated, power-efficient systems-on-chip (SoC) for mobile devices, home entertainment, network and connectivity, automated driving, and IoT. MediaTek’s mission is to provide people all over the world with great technology. By enabling consumer products that help better connect individuals to the world around them, MediaTek empowers people to expand their horizons and more easily achieve their goals. We believe anyone can achieve something amazing. And we believe they can do it every single day. We call this idea Everyday Genius and it drives everything we do.
Are you hoping to fulfill your upcoming summer with engaging activities while having the opportunity to get a glimpse of working in a leading high tech industry? Located in Austin, we are seeking a Physical Design Intern that is capable of thriving in a fast-paced environment. If you are a current student pursuing university degree or a recent graduate that is looking to kick-start your career in advanced CPU & technology, we welcome you to join our internship program for the chance to be part of an exclusive team to take on challenges. At MediaTek, we encourage interns to propose bold ideas to the team and make process improvements.
Apply now and help shape the future of chip design!
Job description
- Responsible for high performance block implementation (RTL to GDSII)
- Perform block level floor planning, pin placement and power grid implementation
- Implement block level placement, CTS and routing
- Close the design to meet timing, power budget and area
- Run physical verification flows (DRC/LVS/EM/IR) and implement fixes to meet the requirements
- Implement ECO’s to address functional bugs, timing and physical verification violations
Required Qualifications
- Candidate must have knowledge in Physical Design Static Timing Analysis
- Ideally candidate should have at least 2 year work experience in physical design or static timing analysis