Job Title: Design Verification Engineer

Location: San Jose, CA (Onsite)

Pay rate -$100/hr on W2

KEY RESPONSIBILITIES:

• Define verification plan, and provide technical direction to execution teams

• Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.

• Create UVM/SystemVerilog based testbenches and tests.

• Make sure that design is bug free.

• Lead Formal verification.

• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

PREFERRED EXPERIENCE:

• IO/PHY knowledge.

• Formal verification expertise.

• Firmware experience.

• Excellent communication, management, and presentation skills.

• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred