Akkodis is seeking a FPGA/ASIC Verification Engineer role is a Contract and Goleta, CA (Remote), We’re ideally looking for an applicant with 8 years of experience with verification methodologies and languages such as UVM and System Verilog.
Pay Range: $105-$109 /hour; The rate may be negotiable based on experience, education, geographic location, and other factors.
Project Overview:
- The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.
Overall Responsibilities:
- As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
- In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.
Top 3 Daily Responsibilities:
Responsibilities include the following:
- UVM/python test development for driving VIPs and other stimulus drivers
- Generation of test components such as monitors, scoreboards and python models
- Coverage closure and GLS bringup and testing
Mandatory Skills/Qualifications: (All skills, both technical and soft, required to be successful in the role)
- Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or a related
- field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and
- SystemVerilog.
- Experience developing and maintaining verification testbenches, test cases, and test
- environments.
- Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations
- Experience in ethernet and SPI required
Non-Essential Skills/Qualifications: (Skills that would be nice to have but are not essential in the role)
- Master’s degree in electrical engineering, Computer Science, or related field.
- UVM/System verilog experience 5+ years (10 + years preferred
- High proficiency in python
- Knowledge of general-purpose operating systems such as Linux and Android.
- Experience in assertions and formal verification preferred
- Experience in ethernet, SPI, AXI, JTAG preferred
- Experience in analog and real number modelling preferred
If you are interested in this role, then please APPLY NOW . For other opportunities available at Akkodis, or any questions, feel free to contact me.
Equal Opportunity Employer/Veterans/Disabled
Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, an EAP program, commuter benefits, and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable. Disclaimer: These benefit offerings do not apply to client-recruited jobs and jobs that are direct hires to a client.
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The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
· The California Fair Chance Act
· Los Angeles City Fair Chance Ordinance
· Los Angeles County Fair Chance Ordinance for Employers
· San Francisco Fair Chance Ordinance