Senior Engineer, Package Design – Milpitas, CA

Description

Socionext America Inc. (SNA)

Socionext Inc. (SNI) is an innovative enterprise that designs, develop and deliver System-on-Chip solutions to customers worldwide. The company is focused on AR/VR, ADAS, imaging, networking, data storage and other dynamic technologies that drive today’s leading-edge applications. Socionext combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, Socionext Inc. is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Socionext America Inc. (SNA), a wholly owned subsidiary of SNI.

We are seeking a Senior Engineer, Package Design to work from our Milpitas, CA office.

Responsibilities

The Package Engineering function provides support, expertise, and insight to the Silicon device development team through preliminary activities of package selection, routing techniques and necessary simulation work. The position involves diverse responsibilities, including evaluation of new packaging technology, package recommendation for custom devices, substrate design support, device/package qualification. You will be reporting to the Director of Package design (USA) and also you will be working very closely with Package/Manufacturing team in our headquarter (Japan),Marketing and Engineering teams located in our Santa Clara office during pre/post sales process.

This position requires experience in the Fabless semiconductor model with a broad knowledge of package technology and manufacturing. Successful candidates will have a deep understanding of a variety of IC package technologies. Candidate should possess specific experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge of Chiplet technology, Optical integrated packages and also experience in extracting/simulating package designs for SI and PI using tools such as HFSS, POWER SI and other leading tools.

Qualifications

Education

Bachelor’s degree in Electrical Engineering, or other semiconductor packaging related discipline

Required Experience And Skills

8 to 10 years of experience in semiconductor packaging design and simulations

Record of success in cross-functional team environment

Good experience with SI/PI tools for package level extraction/simulation

Ability to work with Package Layout engineers

Strong presentation and communication skills

Preferred Experience And Skills

Good knowledge of IC package materials and manufacturing