About the Role

We are seeking a highly skilled and detail-oriented ASIC Design Verification Engineer to join our dynamic team. In this role, you will be responsible for ensuring the functionality, performance, and reliability of complex ASIC designs through rigorous verification processes. You will collaborate closely with design, architecture, and system teams to deliver high-quality ASIC products.

Key Responsibilities

• Develop Verification Plans : Work with design and architecture teams to create comprehensive verification plans based on design specifications.
• Testbench Development : Design and implement advanced UVM/OVM-based testbenches for verifying ASIC modules and full-chip designs.
• Simulation and Debugging : Run simulations, analyze waveforms, and debug failures to identify root causes and ensure functional correctness.
• Coverage Analysis : Perform functional and code coverage analysis to measure verification completeness and identify gaps.
• Automation : Develop and optimize scripts for automation of simulation and regression testing.
• Collaboration : Work closely with cross-functional teams to resolve design and verification issues.
• Documentation : Maintain thorough and clear documentation for test cases, results, and methodologies.

Qualifications

Required Skills and Experience :

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of experience in ASIC design verification.
• Proficiency in hardware description languages like Verilog/SystemVerilog .
• Expertise in using verification methodologies such as UVM , OVM , or VMM .
• Hands-on experience with simulation tools (e.g., Synopsys VCS , Cadence Xcelium , Mentor Questa ).
• Strong debugging skills and familiarity with waveform analysis tools.
• Knowledge of scripting languages such as Python , Tcl , Perl , or Shell for automation.
• Understanding of functional and code coverage methodologies.