About the Role

We are seeking a talented and motivated ASIC RTL Design Engineer to join our cutting-edge development team. As an RTL Design Engineer, you will play a critical role in designing and implementing the digital logic for high-performance ASIC products. You will work closely with cross-functional teams, including architecture, verification, and physical design, to deliver robust, efficient, and high-quality designs.

Key Responsibilities

• RTL Design : Create high-quality Register Transfer Level (RTL) code using Verilog or SystemVerilog based on architectural specifications.
• Micro-architecture Development : Define and document micro-architecture specifications and ensure they align with system requirements.
• Integration : Integrate design components into larger subsystems and verify their functionality.
• Optimization : Optimize designs for performance, power, and area (PPA) while meeting timing constraints.
• Collaboration : Work closely with verification teams to ensure designs meet functional requirements and participate in debug efforts.
• Synthesis and Timing Analysis : Collaborate with physical design teams to support synthesis, static timing analysis, and design closure.
• Documentation : Maintain detailed documentation of design specifications, architecture, and methodologies.

Qualifications

Required Skills and Experience :

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• years of experience in ASIC RTL design and development.
• Proficiency in Verilog and SystemVerilog for RTL design.
• Strong understanding of digital design concepts, including pipelining, clock-domain crossing, and low-power design techniques.
• Experience with synthesis tools (e.g., Synopsys Design Compiler , Cadence Genus ).
• Familiarity with static timing analysis (STA) and timing closure processes.
• Knowledge of debugging tools and methodologies.
• Solid understanding of design for test (DFT) concepts.