Responsibilities:Testbench development - System Verilog UVM and C testsIntegration/development of C tests/APIs and SW build flowIntegration/development of UVM mailboxes and HW/SW communication componentsIntegration of lower level UVM testbenchesTest plan developmentPower Aware testbench development and simulationsSeamless porting between simulation/emulation/prototyping platformsRegression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/ProtoCoverage collection and closureWorking with cross functional teams (DV/Arch/Design/FW) to identify coverage scopeMinimum Qualifications:2-3 years of experience in RTL Design and Verification area, with 2+ years of experience in SoC Design Verification and HW/SW verification, orMaster's Degree in a relevant subject and 1 year of internship and/or verification or design specific projectsKnowledge of System Verilog UVM and vertical testbench integrationKnowledge of low-level HW/SW interaction and debugBasic knowledge of multi CPU and debug architecturesSome experience with development of fully automated flowsPreferred Qualifications:Experience with low-level SW debug - disasm, Tarmac, traceExperience with RISC-V architectureExperience with coresight architectureExperience with embedded SW low-level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, securityExperience with coverage merging across simulation and emulationExperience with Power Aware and Gate Level Netlist in EmulationExperience with development of fully automated flowsExperience with Gate Level SimulationsPython ScriptingAdditional Job Details:C Programming Language (P3 - Advanced)C++ Programming Language (P3 - Advanced)PERL Scripting (P3 - Advanced)Primary Skill:

Python

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