Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities — we're just getting started.

Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day.

We are growing our Machine Learning ASIC Design and µArchitecture team within RL and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using your digital design skills to implement and contribute to the development and optimization of low power machine learning accelerators and state-of-the-art SoCs.

Responsibilities

1. Contribute to ASIC digital µArchitecture and design for low-power interconnect and power management IPs.
2. Assist performance/power analysis of the design and help meet the power and performance targets.
3. Work with architects to map algorithms on the hardware.
4. Support hand-off and integration of blocks into larger SoC environments.
5. Work across disciplines, brainstorm big ideas and build new methodologies.

Minimum Qualifications

1. 5+ years of experience as a Hardware Design Engineer for production silicon shipped in volume.
2. Experience in SoC bus and interconnect protocols.
3. Experience with at least 1 procedural programming language (C, C++, Python etc.).
4. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Preferred Qualifications

1. Experience in SoC integration and ASIC architecture.
2. Knowledge of Physical Design and Low power implementation.
3. Experience with NoC, memory control, DMA uArchitecture.

$142,000/year to $203,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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