Senior Hardware Engineer - Memory Design

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  • Diversity Talent Scouts- Executive Search Firm
Job Summary
Location
Newark ,CA 94560
Job Type
Contract
Visa
Any Valid Visa
Salary
PayRate
Qualification
BCA
Experience
2Years - 10Years
Posted
09 Jan 2025
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Job Description

Senior Hardware Design Engineer responsible for the development of DIMM and custom memory module designs for leading-edge, high-performance server and embedded applications. This job provides the opportunity to work closely with the customers, engineering, manufacturing and test groups. The job requires analytical problem-solving skill, ability to work independently and on multiple projects


Responsibilities:

  • Perform high-speed (10GHz and above) PCB hardware design engineering tasks, including writing design specifications, schematic capture, component selection, collaborating with layout engineers for PCB design, and conducting post-layout SI/PI simulations.
  • Validate designs in the lab to ensure compliance with design requirements.
  • Conduct research as needed to define, specify, and develop products.
  • Perform root-cause analysis to identify issues arising from testing or customer returns.
  • Provide recommendations for product and process improvements and corrections.
  • Foster positive relationships with engineering, manufacturing, and test teams.


Qualifications:

  • BS or MS in Electrical Engineering, or equivalent education and experience.
  • 7+ years of professional experience in high-speed interface work.
  • Strong understanding of electrical engineering principles, analog/digital circuits, and power electronics.
  • Experience with schematic capture using Orcad CIS and working with a centralized part library and design processes.
  • Familiarity with Cadence PCB layout tools and experience in design release, collaborating with layout engineers to determine component placement, routing topology, and design constraints.
  • Solid understanding of PCB design best practices, including stack-up design and impedance control.
  • Experience with post-layout simulations, including signal integrity (SI) and timing analysis, as well as power integrity (PI) simulation.
  • Proficient in using high-speed oscilloscopes and logic analyzers for bring-up, Design Validation Testing (DVT), and troubleshooting.
  • Working knowledge of JEDEC DDR3/DDR4/DDR5 standards.
  • Strong communication skills, both verbal and written, with internal team members and customers, demonstrating logical thinking and a proactive problem-solving approach.

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