• Position: Physical Design (PD) Engineers

• Location: Silicon Valley, USA.

• Experience Levels:

o 8-10 years

o 10-12 years

o 12 + years

Responsibilities:

1. Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.
2. Collaborate across teams (physical design, logic design, package, DFT and test).
3. Hands-on synthesis and PnR using industry standard tools for high-speed digital designs in advanced process nodes.
4. Perform all aspects of sign-off including power, timing, physical verification checks, and design closure.

Experience

1. 8 – 12++ years of experience in Physical Design and timing closure.
2. Hands-on experience in synthesis, PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
3. Must have experience of multiple large SoC tapeouts in advanced nodes including hands-on experience in chip-level physical design and STA closure.
4. Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.