PD Engineers

Responsibilities:

• Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.
• Collaborate across teams (physical design, logic design, package, DFT and test).
• Hands-on synthesis and PnR using industry standard tools for high-speed digital designs in advanced process nodes.
• Perform all aspects of sign-off including power, timing, physical verification checks, and design closure.
• 8 – 12++ years of experience in Physical Design and timing closure.
• Hands-on experience in synthesis, PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
• Must have experience of multiple large SoC tapeouts in advanced nodes including hands-on experience in chip-level physical design and STA closure.
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.

Technology Node:

• TSMC and Samsung
• 7nm, 5nm, 3nm (or lower)