Duration: 06 Months

Job Description:

Senior ASIC Engineer (Static Timing Analysis)

Responsibilities:

Very good communication skills (both written and verbal).

Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)

Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets.

Summarize the regression results periodically to track the progress.

Able to debug the basic issues like SDC loading errors, check_timing (no_clock, unconstrained, no_clock, QoR violations)

Experience:

Minimum of 6-8 years' experience

Worked with EDA tools that enable RTL quality checks

Experience with analyzing the timing reports and identifying both the design and constraints related issues.

Ability to multitask, ramp up quickly on new flows/tools/ideas

Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable

Skills:

Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable

Education:

Bachelor's degree required

About US Tech Solutions:

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Recruiter Details:

Name: Priy Prasang Raj

Email:

Internal Id: 25-30093