Duration: 12+ Months

Job Description:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified

• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases

• Estimate the time required to write the new feature tests and any required changes to the test environment

• Build the directed and random verification tests

• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Preferred Experience:

• Proficient in IP level ASIC verification

• Proficient in debugging firmware and RTL code using simulation tools

• Proficient in using UVM testbenches and working in Linux and Windows environments

• Experienced with Verilog, System Verilog, C, and C++

• Developing UVM based verification frameworks and testbenches, processes and flows

• Automating workflows in a distributed compute environment.

• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

• Scripting language experience: Perl, Ruby, Makefile, shell preferred.

Education:

• Ideally Masters + 5 years or Bachelors + 8 years is preferred

About US Tech Solutions:

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Recruiter Details: Nitesh Singh

Email:

Internal Id: 24-27204