Design Verification Engineer (University Grad)

Location: Sunnyvale, CASalary: $114,000.00-$133,000.00Responsibilities

Strong hands-on DV, SV, and UVM experienceExperience with PCIe is preferredIf not PCIe, experience with any Phy protocol (e.g., DDR phy, USB phy) is acceptableSeniority Level

Mid-Senior levelEmployment Type

Full-timeJob Function

OtherIndustries

IT Services and IT Consulting

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